home *** CD-ROM | disk | FTP | other *** search
/ MacHack 1996 / MacHack 1996.toast / Hacks / Hacks ’92 / RISCy Bitsness / cpu2 / write_buffer.v < prev   
Encoding:
Verilog source code  |  1992-06-18  |  1.1 KB  |  59 lines  |  [TEXT/MPS ]
  1. module write_buffer(reset, clock, addr, write_data, write, read_data, read, read_hit, full, ready, write_data_out, write_addr_out);
  2.     input            reset, 
  3.                     clock,
  4.                     read,
  5.                     write;
  6.     input     [31: 0]addr, 
  7.                     write_data;
  8.     output     [31: 0]read_data,
  9.                     write_data_out,
  10.                     write_addr_out;
  11.     output            read_hit,
  12.                     full,
  13.                     ready;
  14.  
  15.     reg         [31: 0]d[4];
  16.     reg         [31: 0]a[4];
  17.     reg                 v[4];
  18.     reg         [ 3: 0]in,
  19.                     out;
  20.     
  21.     assign full  = v[0] && v[1] && v[2] && v[3];
  22.     assign ready = v[0] | v[1] | v[2] | v[3];
  23.  
  24.     assign read_hit = (v[0] && a[0] == addr) ||
  25.                       (v[1] && a[1] == addr) ||
  26.                       (v[2] && a[2] == addr) ||
  27.                       (v[3] && a[3] == addr);
  28.     
  29.     assign read_data = (v[0] && a[0] == addr ? d[0] :
  30.                         v[1] && a[1] == addr ? d[1] :
  31.                         v[2] && a[2] == addr ? d[2] : d[3]);
  32.                         
  33.     assign write_data_out = d[out];
  34.     assign write_addr_out = a[out];
  35.     
  36.     always @(clock)
  37.     if (~reset) begin
  38.         v[0] = 0;
  39.         v[1] = 0;
  40.         v[2] = 0;
  41.         v[3] = 0;
  42.         in = 0;
  43.         out = 0;
  44.     end
  45.     
  46.     always @(negedge write) begin
  47.         d[in] = write_data;
  48.         a[in] = addr;
  49.         v[in] = 1;
  50.         in = (in+1)&3;
  51.     end
  52.     
  53.     always @(posedge read) begin
  54.         v[out] = 0;
  55.         out = (out+1)&3;
  56.     end
  57.     
  58.     
  59. endmodule